Both are covered by the V4L2 documentation - https://www.kernel.org/doc/html/latest/ ... ocess.html
V4L2_CID_PIXEL_RATE is used with the width, height, V4L2_CID_VBLANK, and V4L2_CID_HBLANK to configure the frame rate - https://www.kernel.org/doc/html/latest/ ... ra-sensors
V4L2_CID_LINK_FREQ is the clock lane frequency on the CSI2 link. Note that as CSI2 clocks data on both clock edges (DDR), it is half the data rate per lane.
It will vary based on the number of lanes in use, the bitdepth, as well as the PLL configuration of the sensor.
THERE IS NO DIRECT RELATIONSHIP BETWEEN THE TWO despite what many developers think.
Many sensors have independent PLLs for the pixel array vs the MIPI block, and as long as the configuration of the two halves is consistent then you can have any relationship between them.
Those two defines are based on the register configuration of the PLLs in the rest of the driver.
V4L2_CID_PIXEL_RATE is used with the width, height, V4L2_CID_VBLANK, and V4L2_CID_HBLANK to configure the frame rate - https://www.kernel.org/doc/html/latest/ ... ra-sensors
V4L2_CID_LINK_FREQ is the clock lane frequency on the CSI2 link. Note that as CSI2 clocks data on both clock edges (DDR), it is half the data rate per lane.
It will vary based on the number of lanes in use, the bitdepth, as well as the PLL configuration of the sensor.
THERE IS NO DIRECT RELATIONSHIP BETWEEN THE TWO despite what many developers think.
Many sensors have independent PLLs for the pixel array vs the MIPI block, and as long as the configuration of the two halves is consistent then you can have any relationship between them.
Those two defines are based on the register configuration of the PLLs in the rest of the driver.
Statistics: Posted by 6by9 — Wed Jul 31, 2024 11:07 am