This interacts poorly with the way the DMA schedules transfers in read-write pairs. One thing we have looked at is sniping DMA writes to DMA registers straight out of the write address phase, skipping the last pipe stage. That would save a cycle in cases like this where you have DMA-dependent DMA controls. It's messy though, so didn't make it onto RP2350.Thank you, LukeW. Well, one cycle is still something.Would have been better if for such uses, the address could be decoded immediately - i.e. having a bit in the DMA channel control reg, which makes it read the first word of input data as a starting address and then changes its own source address to that and only then starts transfer. But it would add some extra logic which can be error prone and slow. And would still not be as fast to start as a single DMA transfer. And would have to reset to the original user-set addr.(where to read the addr from) every new transfer...
Would have been better if for such uses, the address could be decoded immediately - i.e. having a bit in the DMA channel control reg, which makes it read the first word of input data as a starting address and then changes its own source address to that and only then starts transfer. But it would add some extra logic which can be error prone and slow. And would still not be as fast to start as a single DMA transfer. And would have to reset to the original user-set addr.(where to read the addr from) every new transfer...Statistics: Posted by LukeW — Mon Aug 26, 2024 5:36 pm