I think it is well understood that the Pi5's PCIe interface does not meet the spec for operating at Gen3 speeds due out-of-spec jitter on the clock signal.Hi,
These nvme base hats look interesting but do not have access to them, perhaps someone here can answer a question I have.
From what I have read a few people running nvme often at gen3 have seen random errors....
Could this be because of power dips?
Observed error rates will depend on an individual SSD's tolerance to clock jitter.
I don't remember seeing any reports of non-recoverable transport errors, but I choose to run my PCIe at Gen2 as that is quite fast enough for me.
PeterO
Statistics: Posted by PeterO — Tue Sep 10, 2024 8:59 pm