"A Data Memory Barrier (DMB) is an ARM synchronization primitive that ensures memory accesses are observed in the correct order. "I assume you mean "BCM2712". Yes, the data caches are coherent up to and including L3.
You must use appropriate synchronisation primitives (dmb) to ensure that a write on one processor is guaranteed to be visible from another.
I am somewhat familiar with instruction re-ordering, but I have never heard that DATA ACCESS could be re-ordered !
In my case, re-ordering the write would not affect the read on the other processor.
Statistics: Posted by theoldwizard1 — Tue Jan 14, 2025 8:38 pm