Hello!
I'm building my own computer, just by adding a 65C02 processor with an RP2040 clone ("purple") board: https://github.com/SvOlli/sorbus
There the RP2040 is use to provide with an environment for the 65C02 processor, generating the clock, providing RAM, ROM and I/O. The system bus runs on a clock speed of ~1.2MHz. The timing between toggling of the clock is not very precise, because it's depending on what the C code does for each clock cycle.
I already implemented an interface board using another RP2040 running at 133MHz, that sniffes the bus to implement a framebuffer which is then displayed on 32x32 WS2812 LEDs. For this, I only implemented the waiting for the right state of the system bus as PIO code: https://github.com/SvOlli/sorbus/blob/m ... 32/bus.pio
Now, I want to add a sound board that is using yet another RP2040, which listens on the bus and then can simulate a SID for example. The "listening on the bus" part is where I could really use some help now. While the reference implementation just polls the bus using C at 300MHz, I also want to use PIO for this but way more complex that my code above.
The basic setup of the hardware is, that I've got two chip select signals, one needs to be pulled high (GPIO10) and one needs to be pulled low (GPIO11) at the same time. For communication, I've got an 8 bit address bus (GPIO12-19) and an 8 bit data bus (GPIO0-7). CLK is on GPIO8 and R/W (low=write) is on GPIO9. The chip select signals are generated using diodes as "poor man's AND / OR" gates.
To speed things up for CPU reads, I can provide an array of 256 bytes which is keeping the state for each of those 256, much like RAM. However, this needs to be provided at very few clock cycles. I can't use a busy-wait-loop, because that would lock up one of the two cores. To allow to switch to another sound core during runtime, the code cannot be run from RAM, so I'd say overclocking will be only possible up to 240MHz.
Now, for fastest possible handling of the system bus, I'd like to hack up some PIO code. As mentioned, I've done some simple PIO code before, but this is a huge step up, so I'm seeking advice and help here. What I'd like the PIO code to do:
And now to the questions that are going through my mind with this.
Would this work at all?
I'm building my own computer, just by adding a 65C02 processor with an RP2040 clone ("purple") board: https://github.com/SvOlli/sorbus
There the RP2040 is use to provide with an environment for the 65C02 processor, generating the clock, providing RAM, ROM and I/O. The system bus runs on a clock speed of ~1.2MHz. The timing between toggling of the clock is not very precise, because it's depending on what the C code does for each clock cycle.
I already implemented an interface board using another RP2040 running at 133MHz, that sniffes the bus to implement a framebuffer which is then displayed on 32x32 WS2812 LEDs. For this, I only implemented the waiting for the right state of the system bus as PIO code: https://github.com/SvOlli/sorbus/blob/m ... 32/bus.pio
Now, I want to add a sound board that is using yet another RP2040, which listens on the bus and then can simulate a SID for example. The "listening on the bus" part is where I could really use some help now. While the reference implementation just polls the bus using C at 300MHz, I also want to use PIO for this but way more complex that my code above.
The basic setup of the hardware is, that I've got two chip select signals, one needs to be pulled high (GPIO10) and one needs to be pulled low (GPIO11) at the same time. For communication, I've got an 8 bit address bus (GPIO12-19) and an 8 bit data bus (GPIO0-7). CLK is on GPIO8 and R/W (low=write) is on GPIO9. The chip select signals are generated using diodes as "poor man's AND / OR" gates.
To speed things up for CPU reads, I can provide an array of 256 bytes which is keeping the state for each of those 256, much like RAM. However, this needs to be provided at very few clock cycles. I can't use a busy-wait-loop, because that would lock up one of the two cores. To allow to switch to another sound core during runtime, the code cannot be run from RAM, so I'd say overclocking will be only possible up to 240MHz.
Now, for fastest possible handling of the system bus, I'd like to hack up some PIO code. As mentioned, I've done some simple PIO code before, but this is a huge step up, so I'm seeking advice and help here. What I'd like the PIO code to do:
- wait on the system bus for the chip select condition to be met (GPIO10 = high and GPIO 11 = low)
- check if GPIO8 (CLK) is high (bus is stable now), restart if not
- check GPIO9 (R/W) and branch to read and write handler (as seen from system bus)
- the write handler puts address+data in the PIO RX FIFO and triggers an interrupt for C code to handle (fire and forget)
- the read handler triggers an interrupt for C code waits until handler is done, then reads the PIO TX FIFO, switches GPIO0-7 (databus) to output and outputs data from FIFO to GPIO0-7
- at the end, wait for the GPIO8 (CLK) to go low, after that switch GPIO0-7 to input and restart
And now to the questions that are going through my mind with this.
Would this work at all?
- Can I use two different interrupts to skip the checking of data in RX FIFO and make things faster?
- If two different interrups can be done, can a third interrupt be triggered when GPIO12-19 (address bus) are all high? This would be used to switch sound engine, so that could be a write-only register, where read functionality would be "undefined"?
- Is there a chance to use DMA to get the return value out of the 256 bytes array? If yes, would it speed up things?
Statistics: Posted by SvOlli — Sun Mar 23, 2025 7:34 am