Based on imx219, I'd expect to change register 0x114 from 0x01 to 0x03, and then reduce line_length_pix for each mode (largely just halve it).
That'll leave the link frequency as it is, but as you have double the bandwidth a line will take half the time to transmit.
How to convert that into a clean patch is a different matter.
There should be no need to change PLL settings as the sensor supports up to 2.5Gbit/s per lane, so our current settings of 900Mbit/s are fairly tame, and we're relying on the FIFO between pixel array and MIPI block to match the data rates.
IMX219 wanted only 726Mbit/s when in 4 lane mode, vs 912Mbit/s in 2 lane mode.
That'll leave the link frequency as it is, but as you have double the bandwidth a line will take half the time to transmit.
How to convert that into a clean patch is a different matter.
There should be no need to change PLL settings as the sensor supports up to 2.5Gbit/s per lane, so our current settings of 900Mbit/s are fairly tame, and we're relying on the FIFO between pixel array and MIPI block to match the data rates.
IMX219 wanted only 726Mbit/s when in 4 lane mode, vs 912Mbit/s in 2 lane mode.
Statistics: Posted by 6by9 — Wed Apr 02, 2025 11:11 am