Actually it's not so simple, that clock drives PLL synchronizing at the edges, which are working in ns (GHz) domain, here the signal integrity comes crucial. I would go for lower impedance. Have bad reflections? Try to balance like a transmission line.Not that you'll need it at these frequencies (assuming 12 MHz-ish which is almost DC) but rather than a dual output clock generator just feed a single one into two HC04 gates to drive the separate XINs.
I was thinking the same, but you have to take in account the delays and other variable factors,Another thing you can do (if you can spare the pin) is to run the normal xtal oscillator on the first chip, feed the raw 12MHz (before the PLL) out of one of the pins that pinmuxes as CLK_GPOUTx and then feed that pin to XIN on the second RP2xxxx
But all of this depends on the level of synchronization desired, which I haven't seen it specified.
Want to align the internal clocks edges, that would be tough (overclocked tougher), not sure if it's really needed, this might be easier mitigated by other means (software calibration).
Statistics: Posted by gmx — Sat Apr 05, 2025 12:08 pm