First of all, reading the final "conclusions" of reddit post, this "explanation" looks like pure BS:
in contrast with:Just a final update on this - I looked into it further, and the biggest issue was that both cores on the RP2350 share a bus, so even if the memory the cores are accessing does not overlap, they still fight for access to the bus itself. So if a memcpy, or even a DMA transfer is happening on one core, it WILL block the other, no matter what data is being copied. The STM32 does not have that limitation, as it's possible to use separate banks that do not share the same bus. I didn't actually run into the issue on the STM32 because the CPU speed is high enough that the block transfer was finishing before the other core needed to service an interrupt request anyway.
Then it comes to be:The six managers can access any six different crossbar ports simultaneously. So, at a system clock of 150 MHz, the
maximum sustained bus bandwidth is 3.6 GB/s.
I would not count on any of those claims.So with this info I did revisit the RP2350 code, and created a "safe block transfer" function that uses a shared semaphore to perform partial blits when the priority core had just completed its time-critical transfer, since there is a fixed minimum time period until it next needs to service the next PIO request. This solved the issue - though it would mean complicating other code, as any future block moves will also need to adopt this method. In two minds now, as it will complicate development, but the MCU cost is much lower.
Statistics: Posted by gmx — Tue Apr 08, 2025 12:19 pm