I don't see any show-stoppers. A couple of nit-picking points:
a) I think your ground cutout under the 1V1 switcher is larger than necessary. I presume you've done it in the first place to minimise capacitive coupling to the VREG_LX trace (which seems reasonable). However, there's no point excluding the ground under Pin1 of L2 and the positive ends of C19/C20, as those are all deliberately applying capacitance to ground! So personally, I'd make it much narrower.
b) I don't like push-buttons that rely on the on-chip pull-up of the GPIO input: risk of pick-up from outside influences (and hence failing an EMC immunity test). I'd have an explicit pull-up resistor.
Finally, I note that you are supplying the 1V1 regulator from +3V3, rather than VSYS (as allowed by the datasheet, and presumably offering greater efficiency). Was that a deliberate decision to be conservative?
a) I think your ground cutout under the 1V1 switcher is larger than necessary. I presume you've done it in the first place to minimise capacitive coupling to the VREG_LX trace (which seems reasonable). However, there's no point excluding the ground under Pin1 of L2 and the positive ends of C19/C20, as those are all deliberately applying capacitance to ground! So personally, I'd make it much narrower.
b) I don't like push-buttons that rely on the on-chip pull-up of the GPIO input: risk of pick-up from outside influences (and hence failing an EMC immunity test). I'd have an explicit pull-up resistor.
Finally, I note that you are supplying the 1V1 regulator from +3V3, rather than VSYS (as allowed by the datasheet, and presumably offering greater efficiency). Was that a deliberate decision to be conservative?
Statistics: Posted by arg001 — Thu Jun 19, 2025 10:05 pm