I'm setting up a system with a CM5 using the external PCIe lane to transfer audio data (ie a music player) to an FPGA which has up to Gen3 PCIe lanes. This is a lot more than just a player (doing DSP stuff as well).
Since the CM5 does a similar thing with the RP1 I was hoping I could skip the ALSA driver writing and use what is done for the I2S port on the RP1. So it looks like the RP1 is using the Synopsys designware I2S module my idea is to implement the DesignWare I2S registers in the FPGA and hopefully the existing driver can talk to this. Looking trough the databook for the module I understand the registers and how to implement them except for one aspect: how does ALSA tell the hardware what the sample rate is? The I2S module doesn't seem to have an interface for this, it just assumes the rest of the circuit is feeding the proper clk in to the module. In the CM5 implementation there has to be some way that the driver can tell the hardware what the sample rate is.
I found the source for the ALSA and designware c files, they call a function called clk_set_rate but I cannot find any implementation of this function. Any hint as to how this is done and where the source for this is? I presume there is some information sent over the PCIe interface but I can't find out how this is done, or find the source code in the driver that does this.
Thanks,
John S.
Since the CM5 does a similar thing with the RP1 I was hoping I could skip the ALSA driver writing and use what is done for the I2S port on the RP1. So it looks like the RP1 is using the Synopsys designware I2S module my idea is to implement the DesignWare I2S registers in the FPGA and hopefully the existing driver can talk to this. Looking trough the databook for the module I understand the registers and how to implement them except for one aspect: how does ALSA tell the hardware what the sample rate is? The I2S module doesn't seem to have an interface for this, it just assumes the rest of the circuit is feeding the proper clk in to the module. In the CM5 implementation there has to be some way that the driver can tell the hardware what the sample rate is.
I found the source for the ALSA and designware c files, they call a function called clk_set_rate but I cannot find any implementation of this function. Any hint as to how this is done and where the source for this is? I presume there is some information sent over the PCIe interface but I can't find out how this is done, or find the source code in the driver that does this.
Thanks,
John S.
Statistics: Posted by johnswenson1 — Wed Jun 25, 2025 1:19 am