Hi Gustavo, thanks for your latest example code. Only one change was required to run it on RP2350, which uses system clock of 150 MHz by default, see output below:I am not sure if the two lines to power up the PLLs (PO and VCOPO) again are necessary here, because they were probably not powered down.
From the datasheet however, the recommended procedure apparently is to switch the system clock to another source temporarily, then make the changes to the PLLs, before bringing them back up and wait for them to stabilize, before switching the system clock source back.
I may do some experiments with overclocking above 150 MHz which may require increasing VRef for stable operation. According to [1], RPi Pico 2 reportedly works reliably with 570 MHz at 1.7 V. Even higher clock frequencies can be achieved by raising VRef but require passive or active cooling. This comes in handy while using pairs of PIO outputs as local oscillators (LO) that generate I/Q signals to drive complex multipliers/mixers of Software Defined Radios (SDR), such as for ex. Tayloe Quadrature Sampling Detectors (QSD) and Exciters (QSE) [2].[1] Overclocking Raspberry Pi Pico 2 https://learn.pimoroni.com/article/over ... the-pico-2
[2] Ultra Low Noise, High Performance, Zero IF Quadrature Product Detector and Preamplifier by Dan Tayloe https://www.norcalqrp.org/files/Tayloe_mixer_x3a.pdf
Code:
- vregCtrlStatus := rp.VREG_AND_CHIP_RESET.VREG.Get() // RP2040: Voltage regulator control and status+ vregCtrlStatus := rp.POWMAN.GetVREG_VSEL() // RP2350: Voltage regulator control and statusFrom the datasheet however, the recommended procedure apparently is to switch the system clock to another source temporarily, then make the changes to the PLLs, before bringing them back up and wait for them to stabilize, before switching the system clock source back.
I may do some experiments with overclocking above 150 MHz which may require increasing VRef for stable operation. According to [1], RPi Pico 2 reportedly works reliably with 570 MHz at 1.7 V. Even higher clock frequencies can be achieved by raising VRef but require passive or active cooling. This comes in handy while using pairs of PIO outputs as local oscillators (LO) that generate I/Q signals to drive complex multipliers/mixers of Software Defined Radios (SDR), such as for ex. Tayloe Quadrature Sampling Detectors (QSD) and Exciters (QSE) [2].
Code:
Raspberry Pico adjust_clock_V3, adapted to RP2350: Read Voltage Regulators RegistersVoltage Regulator Register Value: 0x0000000B Voltage Select = 0x0 -> 0.80 VRead PLL SYS RegistersReference Clock Divider Value: 1 PLL SYS Feedback divisor: 125 PLL VCO frequency: 1500 MHz PLL SYS post divider 1: 5 PLL SYS post divider 2: 2 PLL SYS - System Clock frequency: 150 MHz PLL SYS - Adjusting clock settingsRead PLL SYS RegistersReference Clock Divider Value: 1 PLL SYS Feedback divisor: 125 PLL VCO frequency: 1500 MHz PLL SYS post divider 1: 6 PLL SYS post divider 2: 2 PLL SYS - System Clock frequency: 125 MHz Core temperature: 23.86℃Core temperature: 23.86℃Core temperature: 24.33℃Core temperature: 23.86℃[2] Ultra Low Noise, High Performance, Zero IF Quadrature Product Detector and Preamplifier by Dan Tayloe https://www.norcalqrp.org/files/Tayloe_mixer_x3a.pdf
Statistics: Posted by hb9cwp — Fri Jul 18, 2025 9:09 am