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Interfacing (DSI, CSI, I2C, etc.) • Bringup DSI display with EK79007 (again)

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I have been trying to bring up a DSI display for the CM4, currently without success.

It uses display controller EK79007AD3. I know there have been some attempts at making displays with this chip work (without success):

viewtopic.php?t=361578
viewtopic.php?t=333262

I managed the following steps:
- Communicate with the EK79007 chip for setup commands.
- Get the BIST mode to work (Display shows built-in pattern), with secret command reg 0x87 := 0x5A.

The display is connect on a custom board to the DSI1 port.

I tried a lot of different timing configurations from the topics above and the manufacturer provided ones. Display always stays black.

I know, that the panel as well as the board design should work, because I have a working solution. I just switched the module to the CM5.

With the CM5 (almost?) all timing configurations work correctly:
- The ones with the default timings of the datasheet.
- The ones I got from the manufacturer.
- The adjusted ones for the discrete pix clocks from the RPI4 found in the topics above.
- A 2-lane configuration (tried 50Hz and 30Hz (pix clock 25000)).

Also different video modes work:
  • Burst Mode (MIPI_DSI_MODE_VIDEO_BURST)
  • Sync Pulse (MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
The rp1 driver for the CM5 seems to implement these options (while the vc4_dsi does not and is implicitly burst mode). The manufacturer also confirmed that they tested both modes with their test setup based on the SSD2828QN4 Master bridge.

The implementation based on the rpi-6.12.y can be found here: drivers/gpu/drm/panel/panel-goworld-dm20502.c

Relevant timing (one of the implemented options).

Code:

// manufacturer provided valuesstatic const struct drm_display_mode gw_values_display_mode_4lane = {.clock = 50000, /* -> refresh rate is 59.72 Hz */.hdisplay = 1024,.hsync_start = 1024 + 112,    // frontp.hsync_end = 1024 + 112 + 8, // HSPW = hor sync pulse width.htotal = 1024 + 112 + 8 + 160, // hbp.vdisplay = 600,.vsync_start = 600 + 9,      // frontp.vsync_end = 600 + 9 + 3,   // VSPW vert sync pulse width.vtotal = 600 + 9 + 3 + 30, // vbp/* syncs are active low, but this should be default/normal ?*/.flags =  DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,};static const struct panel_desc goworld_dm20502_panel_desc_4lanes_gw = {.mode = &gw_values_display_mode_4lane,.bpc = 8,.size = {.width = 155,.height = 86,},/* Sync pulse mode is proven to work: Burst Mode also should work/works on CM5.CM4 driver does not implement it (always burst mode?), only CM5 driver, see https://forums.raspberrypi.com/viewtopic.php?p=2272127#p2272127*/// .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM,.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM,.format = MIPI_DSI_FMT_RGB888,.lanes = 4,};
I also have access to parts of the manufacturers test/setup code for the SSD2828QN4 (PHY Master configuration, DSI mode and timing configuration, PHY min/max timings). I tried to match these in the vc4_dsi driver, where the min timings seemed different. No success.

There were also some mentions about different flags for the vc4_dsi driver regarding the exact packets to send (LP, Blanking, Null packets), which I tried to change, without success.

Adjusting these are not easily doable without documentation of the DSI peripheral.

Any ideas what i can try? What are the differences between the CM5 and CM4 communications?

PS: the whole SW stack is based on yocto/meta-raspberrypi, I did not use the RPI OS.

Statistics: Posted by mwauer — Wed Jul 30, 2025 10:29 am



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