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HATs and other add-ons • 2 x SC16IS752 on different SPI's

Hi all.
I have a suspicion that needs confirmation Image may be NSFW.
Clik here to view.
:)


As the subject says, I'm trying two SC16IS752 chips on SPI0 and SPI1 to make four UARTs.
Since I had no luck with some Waveshare HATs I acquire some OEM / NoName board that have required configuration.

I've added SPI related lines in config.txt

Code:

dtparam=spi=ondtoverlay=sc16is752-spi0,int_pin=25dtoverlay=sc16is752-spi1,int_pin=24
and rebooted

After reboot dmesg shows SPI devices with serial ports

Code:

$ dmesg | grep spi[   67.027439] spi0.0: ttySC0 at I/O 0x0 (irq = 160, base_baud = 921600) is a SC16IS752[   67.043103] spi0.0: ttySC1 at I/O 0x1 (irq = 160, base_baud = 921600) is a SC16IS752[   67.062561] spi1.0: ttySC2 at I/O 0x0 (irq = 161, base_baud = 921600) is a SC16IS752[   67.064151] spi1.0: ttySC3 at I/O 0x1 (irq = 161, base_baud = 921600) is a SC16IS752
there are interrupts

Code:

$ cat /proc/interrupts | grep spi 53:          0  ARMCTRL-level  61 Edge      20215080.spi 78:          0  ARMCTRL-level  86 Edge      20204000.spi160:          0  pinctrl-bcm2835  25 Level     spi0.0161:          0  pinctrl-bcm2835  24 Level     spi1.0
and also two gpiochips 1 and 2 showed up in /dev

Code:

$ ls -l /dev/gpio*crw-rw----+ 1 root gpio 254, 0 Apr  9 14:23 /dev/gpiochip0crw-rw----+ 1 root gpio 254, 1 Apr  9 14:24 /dev/gpiochip1crw-rw----+ 1 root gpio 254, 2 Apr  9 14:24 /dev/gpiochip2lrwxrwxrwx  1 root root      9 Apr  9 14:23 /dev/gpiochip4 -> gpiochip0
so four serial ports became available

Code:

$ ls -l /dev/ttyS*crw-rw---- 1 root dialout   4, 64 Apr  9 14:23 /dev/ttyS0crw-rw---- 1 root dialout 239,  0 Apr  9 14:24 /dev/ttySC0crw-rw---- 1 root dialout 239,  1 Apr  9 14:24 /dev/ttySC1crw-rw---- 1 root dialout 239,  2 Apr  9 14:24 /dev/ttySC2crw-rw---- 1 root dialout 239,  3 Apr  9 14:24 /dev/ttySC3
and pinctrl and gpioinfo also seems that have all that SPI communication needs, MISO MOSI SCLK and everything

Code:

$ pinctrl | grep SPI 9: a0    -- | lo // GPIO9 = SPI0_MISO10: a0    -- | lo // GPIO10 = SPI0_MOSI11: a0    -- | lo // GPIO11 = SPI0_SCLK19: a4    -- | lo // GPIO19 = SPI1_MISO20: a4    -- | lo // GPIO20 = SPI1_MOSI21: a4    -- | lo // GPIO21 = SPI1_SCLK

Code:

$ gpioinfo | grep spiline   7:      "GPIO7"   "spi0 CS1"  output   active-low [used]line   8:      "GPIO8"   "spi0 CS0"  output   active-low [used]line  18:     "GPIO18"   "spi1 CS0"  output   active-low [used]line   7:      "GPIO7"   "spi0 CS1"  output   active-low [used]line   8:      "GPIO8"   "spi0 CS0"  output   active-low [used]line  18:     "GPIO18"   "spi1 CS0"  output   active-low [used]
With all of the above, I assumed that I can now test serial ports so I started some python program to initialize those ports and periodically send something on each one of them. Python did not return any error and started looping. But there is no Rx Tx led indications on the SC16IS752 outputs on any port.
I checked interrupts again and periodically they was increasing while Python runs.

Code:

$ cat /proc/interrupts | grep spi 53:        286  ARMCTRL-level  61 Edge      20215080.spi 78:         95  ARMCTRL-level  86 Edge      20204000.spi160:          0  pinctrl-bcm2835  25 Level     spi0.0161:          8  pinctrl-bcm2835  24 Level     spi1.053:        322  ARMCTRL-level  61 Edge      20215080.spi 78:        107  ARMCTRL-level  86 Edge      20204000.spi160:          0  pinctrl-bcm2835  25 Level     spi0.0161:          8  pinctrl-bcm2835  24 Level     spi1.053:        839  ARMCTRL-level  61 Edge      20215080.spi 78:        276  ARMCTRL-level  86 Edge      20204000.spi160:          0  pinctrl-bcm2835  25 Level     spi0.0161:         20  pinctrl-bcm2835  24 Level     spi1.0
Now I'm pretty sure that on the RPi side, both HW and SW related, everything is OK and that I must pull out my oscilloscope and logic analyzer to debug connections and communications between RPi GPIO header and SC16IS752 chips.

Am I right or am I missing something on the RPi side?

Thanks

Statistics: Posted by freedom74 — Thu Apr 10, 2025 12:49 pm



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