To disable all maskable interrupts with the SDK:But that does the same as your current code though: CPSID I.
Even though you've used copy_to_ram, so this likely isn't the issue, you can configure the core 1 MPU to cause a hard fault if the flash memory port is ever accessed by core 1. That might give you more confidence that is not the issue. The flash memory port can cause core 1 to stall waiting for core 0, despite having higher arbitration priority, for example if core 0 causes a XIP cache miss and core 1 later tries to use the flash port while the cache line is still being filled.
Can you share the code for the core 1 loop?
Given what core 1 is doing, I assume core 1 isn't acquiring any locks or other synchronization objects that core 0 might hold?
As an alternative approach, I did something similar to this but used PIO and the DMA controller to perform the IO read and IO write requests for 8080 bus. PIO state machines are much less susceptible to jitter than the processors.
The general idea is to have a PIO state machine pull an address off the bus and push it to the DMA controller, which writes it to the READ_ADDR another DMA channel and then chains to that channel to perform the read from memory. It might not be possible to do that in 50ns but thought I would mention it in case useful.
https://github.com/alastairpatrick/pico ... /sys80.pio
Code:
save_and_disable_interrupts();Even though you've used copy_to_ram, so this likely isn't the issue, you can configure the core 1 MPU to cause a hard fault if the flash memory port is ever accessed by core 1. That might give you more confidence that is not the issue. The flash memory port can cause core 1 to stall waiting for core 0, despite having higher arbitration priority, for example if core 0 causes a XIP cache miss and core 1 later tries to use the flash port while the cache line is still being filled.
Can you share the code for the core 1 loop?
Given what core 1 is doing, I assume core 1 isn't acquiring any locks or other synchronization objects that core 0 might hold?
As an alternative approach, I did something similar to this but used PIO and the DMA controller to perform the IO read and IO write requests for 8080 bus. PIO state machines are much less susceptible to jitter than the processors.
The general idea is to have a PIO state machine pull an address off the bus and push it to the DMA controller, which writes it to the READ_ADDR another DMA channel and then chains to that channel to perform the read from memory. It might not be possible to do that in 50ns but thought I would mention it in case useful.
https://github.com/alastairpatrick/pico ... /sys80.pio
Statistics: Posted by alastairpatrick — Sat Apr 20, 2024 6:28 pm